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Interface Descriptions
Table 3-3 ? Control and Status Signals (continued)
Port Name
Type
Description
CMDSYNC
MSGSTART
SYNCNOW
BUSRESET
INTOUT
INTVECT[6:0]
Out Pulses HIGH for a single clock cycle when the RT detects the start of a 1553B
command word (or status word) on the bus. Provides an early signal that the RT
may be about to receive or transmit data or mode code.
Out Pulses HIGH for a single cycle when the RT is about to start processing a 1553B
message whose command has been validated for this RT.
Out Pulses HIGH for a single clock cycle when the RT receives a “synchronize” (with or
without data mode) command. The pulse occurs just after the 1553B command
word (sync with no data) or data word (sync with data mode code) has been
received.
Out Pulses HIGH for a single clock cycle whenever the RT receives a “reset mode”
command. The core logic will also automatically reset itself on receipt of this
command.
Out Goes HIGH when data has been received or transmitted or a mode command
processed. The reason for the interrupt is provided on INTVECT. This output will
stay HIGH until INTACK goes HIGH. If INTACK is held HIGH, this output will pulse
HIGH for a single clock cycle.
Out This 7-bit value contains the reason for the interrupt. It indicates which subaddress
data has been received or transmitted.
Bit 6:
Bit 5:
Bits 4:
0: Bad block received
0: RX data
0:Subaddress
1: Good block received
1: TX data
Further information can be found by checking the appropriate transfer status word
for the appropriate subaddress.
INTACK
In
Interrupt acknowledge input. When HIGH, this resets INTOUT back to LOW. If this
input is held HIGH, the INTOUT signal will pulse HIGH for one clock cycle every
time an interrupt is generated.
MEMFAIL
Out Goes HIGH if the core fails to read data from or write data to the backend interface
within the required time. This can be caused by the backend not asserting
MEMGNTn fast enough or asserting MEMWAITn for too long.
CLRERR
In
Used to clear MEMFAIL and other internal error conditions. Must be held HIGH for
more than two clock cycles.
TESTTXTOUT In
FSM_ERROR Out
This input is for test use only. It should be tied LOW.
When HIGH and the TESTTXTOUTEN parameter is set to 1, the RT will transmit
more than 32 data words if a “transmit data” command word is received. This will
cause the RT to shut down the transmitter and set the TIMEOUT bits in the BIT
word.
This output will go HIGH for a single clock cycle if any of the internal state
machines enter an illegal state. This output should not go HIGH in normal
operation. Should it go HIGH, it is recommended that the core be reset.
PURSTN
BITINEN
BITIN[15:0]
In
In
In
Asynchronous power-up reset input (active low) that is used to initialize the last
status word value. This input is valid only when the parameter INITLASTSW = 1.
Transmit bit word enable input (active high). This input is valid when parameter
EXTERNAL_BIST = 1 (to support mode code 19).
Transmit bit word input. This input is valid when the parameter EXTERNAL_BIST =
1.
Note: All control inputs except RSTn are synchronous and sampled on the rising edge of the clock. All
status outputs are synchronous to the rising edge of the clock.
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